1. Field of the Invention
This invention pertains generally to chip-to-chip communications, and more particularly to a serializer and de-serializer based on quadrature amplitude modulation (QAM) at multiple frequencies.
2. Description of Related Art
Conventional serial/de-serial I/O is based on multiplexing and demultiplexing digital communications. Using these conventional schemes to increase communications bandwidth requires increasing clock rate. Because a given process technology has its own limitations on clock rates, one must often increase the number of I/O connections to increase the bandwidth, whereby the I/O bandwidth increase comes at the expense of higher manufacturing costs. These costs are even further increased in 3D integrated circuit integration, such as those based on through-substrate-via (TSV) for vertical interconnections. The number of TSVs for the I/O is non-scalable due to fundamental physical or mechanical constraints. Higher than a certain number of TSVs per unit area (or population density) leads to thinned Si substrate (about 100 μm/tier) which can result in collapse. Therefore, this thinning can seriously limit inter-tier communication bandwidth in 3D integrated circuits.
Accordingly, a need exists for chip-to-chip communication circuits having higher communication bandwidths without a concurrent need for increased clock rates or additional I/O connections. The present invention fulfills that need, and overcomes the shortcomings of previous chip-to-chip communications topologies.